The first two slides show raw data captured on a PC using a USB to serial converter. Q13 occurs as the stop bit for data in 8-N-1 serial format, 2400 baudĪnd Q12 along with Q13 occur as the stop bits for data in 7-N-2 serial format, 2400 baudĪ diode resistor gate is used to simplify combination the outputs from the shift-register and decoder to form the final serial output. Q4-bar AND QH of the shift-register occur at the '0','1' position of the serial Hex 30,31 With reference to the oscilloscope trace of the serial-output: The decoder outputs Q4-Q14 are the basic 10 counter clock periods used for the serial output generation. The 74LS154 4 -16 line decoder inputs are connected to the QA-QD outputs of the 4-bit binary counter. The UNL2003 along with two OR gates forms an 8-bit OR gate which ensures that a High state is input to the shift-register if all the outputs are zero. The LFSR scheme has a drawback that no sequence is generated if the seed is all zeroes. The resistor network sets the Low value for unconnected er-OR gate inputs, as open TTL inputs are considered as H. Effectively the connected switches are ex-OR'ed to form the feedback input to the shift-register. The eight outputs of the shift-register are connected to ex-OR gates through DIP switches. QD of the counter when inverted forms the clock to the 8-Bit shift register 74LS164. This clock is fed to the 74LS93 4-bit binary counter. The 555 timer sets-up the primary clock at 2400 Hz.
The circuit is implemented using standard TTL devices a 555 timer and an ULN2003 open-collector driver. I wish to acknowledge the use of the online OMNI LFSR calculator used in verification of the hardware results. This is suggested as a starter project to students for implementation on FPGA kits where both the LFSR and serial-data output are implemented. Generation of different length PN sequences including the maximally long LSFR could be demonstrated and compared with calculated results. This permitted acquiring and analyzing the output stream using a simple dumb terminal.Ī 8-bit DIP switch permits setting up of desired feedback combinations from the eight shift register outputs. Additional circuitry was added to convert and send the 1's and 0's output of the LFSR as ASCII serial data '30','31' Hex. This project implements a pseudo-random (PN) sequence generator based on a 8-bit linear-feedback shift register (LFSR). Surprisingly the breadboard hardware which was recently returned to me and had not been powered for 30 odd years worked perfectly when powered ON. This is revisit of a student project I mentored back in 1990-91.
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